The present invention relates generally to electronic ballasts for powering discharge lamps. More particularly, the present invention relates to ballast circuitry designed to prevent startup flash when a ballast starts up from a low level dimming current.
Dimming electronic ballasts are popular in the lighting market because of their ability to adjust light output levels and save energy. Sometimes if a dimming ballast is not properly designed a light flash may be seen when starting from minimum level dimming. This light flash may be quite annoying to the user.
Referring now to FIG. 1, an electronic ballast 1 having a typical class D inverter topology for powering a fluorescent lamp 12 as known in the prior art is shown. Q1 and Q2 are switching elements, typically MOSFETs, in a half bridge inverter 18. C1 is a DC blocking capacitor. T1 is a resonant inductor, and C2 is a resonant capacitor. C3 is another DC blocking capacitor. A ballast control driver circuit 14 is used to control the operating frequency of the switching elements Q1 and Q2 of the half bridge inverter 18. Usually this driver circuit is an integrated circuit 14, where there is a pin 16 for a voltage controlled oscillator input and a capacitor C4 is connected to this pin 16. The voltage across the capacitor C4 is the input for the voltage controlled oscillator that controls the operating frequency of the half bridge inverter 18.
Referring to FIGS. 2a-2c, operation of the prior art electronic ballast 1 may be further described. When 0≦t≦t1, voltage controlled oscillator input (V_vco_in) is V_min; integrated circuit output frequency is F_max; and lamp current I_lamp is zero. Typically this period is designated for preheating of the lamp 12.
When t1≦t≦t2, preheating of the lamp is completed. The integrated circuit 14 will attempt to start the lamp 12. To do so, the integrated circuit 14 will have to reduce the inverter operating frequency by charging up the capacitor C4 until the output voltage reaches the lamp ignition breakdown voltage at t2. At t=t2, the lamp breaks over and current is ready to flow. During this period the lamp current I_lamp is still zero.
When t2≦t≦t3, the integrated circuit continues charging capacitor C4 until the voltage controlled oscillator input V_vco_in reaches V_max. During this period the frequency continues to decrease and lamp current increases from zero to I_startup_peak.
When t3≦t≦t4, the integrated circuit starts to discharge capacitor C4 until the lamp current equals the steady state current (I_lamp=I_steady).
Generally the period between t2 and t3 is long (i.e. 10 ms to 50 ms) such that a visible flash will be seen if the steady state current I_steady is very low. Typically the time between t3 and t4 is short because the integrated circuit rapidly discharges the capacitor C4 after the voltage controlled oscillator input V_vco_in reaches V_max. Therefore, the time between t2 and t3 may be the primary cause for the visible flash that occurs during lamp startup.
In light of the previously described problems, it would be desirable to have an electronic ballast that prevents the visible flash at startup under low current dimming conditions.